As is known in the art, an important requirement for any Radio Frequency (RF) Transistor Amplifier Design is the establishment of stable DC operating conditions. Such conditions affect many of the amplifier performance characteristics, e.g., gain, frequency response, noise and efficiency. Also the DC operating conditions, e.g., quiescent drain current, must be predictable and invariant with respect to temperature, power supply and process variations. Setting this quiescent drain current (Id) for a Field Effect Transistor (FET) type amplifier, shown in FIG. 1, is usually accomplished by adjusting the DC voltage Vg supplied to the gate of the transistor (Q1). Although in principle Vg can be determined readily from the Id versus Vg transfer characteristic of a typical device, inherent sensitivities of the FET characteristics to fabrication process and temperature preclude use of a fixed Vg.
As is also known in the art, a commonly used DC biasing element in analog circuit design is a current mirror such as that described in a book by Paul R. Gray and Robert G. Meyer, entitled Analysis and Design of Analog Integrated Circuits, 3rd ed., New York: Wiley, 1993. FIG. 2 is a schematic representation of a current mirror for D-mode GaAs MESFET operational amplifiers demonstrated by Scheinberg, see N Scheinberg, Design of high speed operational amplifiers with GaAs MESFETs, procs 1987 IEEE ISCAS (Philadelphia), May 1987, pp 193-198 and C. Tamazou and D. Haigh, “Gallium Arsenide Analog Integrated Circuit Design Techniques,” Chapter 8 in “Analogue IC design: the current-mode approach”, Edited by C. Toumazou, F. J. Lidgey & D. G. Haigh. London: Peter Peregrinus Ltd. 1990. By appropriately sizing; i.e., widths of the transistors Q1 and Q2, the current mirror allows one to set very stable and controllable current ID2 in the main circuit transistor Q2. Here, the current ID2 “mirrors” (i.e., is proportional to) the reference current Iref. An important element to the operation of the current mirror is availability of a stable reference current, Iref. This relationship of the currents is shown by the following equation where.ID2=(Width Q2/Width Q1)Iref
Note that as long as Q1 and Q2 are fabricated in proximity to each other on the same chip, the relationship between the currents will be maintained regardless of process variation, most notably voltage threshold (Vt) variations.
The above circuit in FIG. 2 can be easily Implemented for controlling drain current in a high efficiency, high powered RF amplifier. FIG. 3 shows a simplified schematic implementation with appropriate inductor and capacitors connected to what would be a RF amplifier FET(s) Q2. A necessity for high power and high efficiency RF amplifiers is that the FET source potentials need to be tied directly to ground reference, also depicted in FIG. 3 by showing Vss tied to ground potential. Also note that Vss1 is more negative than ground potential where the drains of Q1, Q2 and Q3 are more positive than ground potential.
In the absence of a bias circuit that compensates for process variations, some means for adjusting the gate voltage Vg preferably on a per amplifier basis has to be implemented to ensure that quiescent drain current Id is set near the nominal target value. Typical implementations include: supplying externally an individual Vg voltage to each amplifier; adding a resistor ladder network on chip to generate several candidate Vg voltages from a fixed, supply voltage; screening and dividing parts into several Vg bins. However, these options require some level of testing to determine first how each part or a group of parts has to be biased. Then assembly is tailored to that particular part or group of parts. These steps add significant time and cost to the product. One of the goals of a DC bias circuit is to circumvent the need for these Vg bins. Examples of patents for these types of circuits are: U.S. Pat. Nos. 5,889,429; 6,304,130; 6,114,901; 5,793,194; 4,896,121; and 7,928,804.
As is also knows in the art, high performance RF amplifiers are typically fabricated in III-V FET technology. GaAs or GaN for example. In contrast to the silicon-based technologies (CMOS), “biasing” current mirrors are not common in III-V FET amplifiers due to the absence of monolithic high precision constant current sources to generate Iref. CMOS, for example, can rely on the high level of control over the technology threshold voltage (Vt) for generating these references.
The inventors have recognized that for III-V FET technology, one can utilize a semiconductor resistor operated (i.e., placed) in saturation (i.e., in a region where the current through the resistor is substantially constant with variations in the voltage across the resistor) to generate Iref as shown in FIG. 3. A saturated resistor has similar current—voltage behavior as a FET when the resistor operates in saturation and thereby enables the semiconductor resistor to operate as a constant current source; i.e., constant current over varying supply voltage. The advantage of the saturated resistor is it is less prone to process variations than FET based constant current sources, making it an ideal monolithic current reference. The inventors have recognized that formation of the Schottky Gate is the primary reason the FET current reference is prone to more variability than the resistor reference, see Chien-Ping Lee, Bryant M. Welch, and Ricardo Zucca, Saturated Resistor Load for GaAs Integrated Circuits, IEEE Transactions on Microwave Theory and Technique, Vol. MTT-30, No. 7, July 1982. FIG. 4 is a chart depicting the current-voltage relationship of a semiconductor resistor operated in saturation. It is noted that, as a function of voltage across the resistor, the resistor passes from a linear region where the current through the resistor is directly proportional to the voltage across the resistor to a transition region to the saturation region where the current through the resistor is substantially constant with variations in the voltage across the resistor
In accordance with the present disclosure, a current mirror circuit is provided having formed in a semiconductor: a pair of transistors arranged to produce an output current through an output one of the transistors proportional to a reference current fed to an input one of the pair of transistors; a resistor comprising a pair of spaced electrodes in ohmic contact with the semiconductor, one of such pair of electrodes of the resistor being coupled to the input one of the pair of transistors; and circuitry for producing a voltage across the pair of electrodes of the resistor to place the resistor into saturation producing a current through a region in the semiconductor between the pair of spaced ohmic contacts, such produced current being fed to the input one of the transistors as the reference current for the current mirror.
In one embodiment, an amplifier circuit is provided having formed in a semiconductor current mirror circuitry comprising: a field effect transistor having: a gate electrode; a source electrode and a drain electrode, the gate electrode being coupled to a negative potential; the source electrode being coupled to ground potential; and the gate electrode being coupled to a variable input signal, the input signal being amplified by the transistor to produce an amplified signal at the drain electrode; wherein the current mirror produces current in the drain electrode proportional to a reference current produced by the current mirror, the current mirror comprising: a resistor comprising a pair of spaced electrodes in ohmic contact with the semiconductor; and circuitry for producing a voltage across the pair of electrodes of the resistor, such circuitry placing the resistor into saturation, such produced current being fed to drain electrode to provide the reference current.
With such an arrangement, because the resistor is a two terminal device, the use of a three terminal FET based constant current source having Schottky contact gate formation has been eliminated along with the process variability associated with such Schottky gate formation. Thus, the saturated resistor constant current source according to the disclosure has less process variation than a three terminal FET based constant current source.
The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will be apparent from the description and drawings, and from the claims.
Like reference symbols in the various drawings indicate like elements.